The present invention concerns a method for operating a passive-matrix addressable ferroelectric or electret memory device wherein said memory device comprises one or more arrays or matrices with memory cells in the form of a ferroelectric or electret thin-film polarizable material exhibiting hysteresis, particularly a ferroelectric or electret polymer thin film, and a first and second set of respective parallel electrodes, wherein the electrodes of the first set forming word lines (WL) in the device, are provided in substantially orthogonal relationship to the electrodes of the second set forming bit lines (BL) in the device, wherein the electrodes of said first and second set are provided in direct or indirect contact with the thin-film material of the memory cells, whereby a polarization state in individual memory cells can be read, erased or written by applying appropriate voltages to the individual electrodes of respectively said first and second set of electrodes, wherein the method implements a voltage pulse protocol based on a one-third voltage selection rule whereby non-addressed cells are subjected to disturbing voltages across them not exceeding approximately ⅓ of the switching voltage Vs, wherein the voltage pulse protocol comprises a read cycle and a write/erase cycle respectively with time sequences of voltage pulses of predefined amplitudes, polarities and lengths, wherein the read cycle comprises applying a set of voltage differences to electrodes of respectively said first and second set of electrodes in case data are read out from the memory cells, and wherein the write/erase cycle comprises steps for applying another set of voltage differences to electrodes of respectively said first and second set of electrodes.
The relevant device configuration as described above is well known in the prior art, and is generally referred to as a passive matrix-addressed memory. As shown in FIG. 1, it is typically implemented by letting two sets mk(k=1→x), n1(l=1→y) of parallel electrodes cross each other, normally in an orthogonal fashion, in order to create a matrix of cross-points that can be individually accessed electrically by selective excitation of the appropriate electrodes from the edge of the matrix. A layer S of a functional (e.g. storage) medium of ferroelectric or electret material is provided between or over the electrode sets such that the capacitor-like structures 2kl (functioning as memory cells) are formed in the material between or at the crossings of the electrodes m,n. This is shown in detail in FIG. 2, where a cell 2kl is formed in the overlap regions 3 and 4 between electrodes mk and n1, respectively. Selection of individual cells in the matrix is illustrated in FIG. 3. In conformity with standard usage, each horizontal electrode shall henceforth be termed a Word Line (WL), and each vertical electrode a Bit Line (BL). Furthermore, the electrodes employed in the electrical selection of a single cell or a set of cells in the matrix shall be termed an Active Word Line (AWL) and an Active Bit Line (ABL). When applying potential differences between an AWL and an ABL, the ferroelectric or electret material in the selected cell is subjected to an electric field which generates a polarization response generally tracing a hysteresis curve or a portion thereof, (cf. below). By manipulating the direction and the magnitude of the electric field, the memory cell can be left in a desired polarization state corresponding to a certain logic value. The passive addressing of this type of arrangement leads to simplicity of manufacture and a high density of cross-points.
The use of ferroelectrics or electrets as memory materials confers non-volatility upon the memory devices in question, due to their ability to retain a logic state in the absence of applied voltages or currents to the memory device. This attribute of ferroelectrics in particular is known and attempts have been made to exploit it in prior art memory devices. It is based on the fact that these electrically polarizable materials possess at least two equilibrium orientations of the spontaneous polarization vector in the absence of an external electrical field. The spontaneous polarization vector may be switched between these two orientations by an electric field. One of the polarization states is considered to be a logic “1” and the other state a logic “0”. Referring to FIG. 4, a material with a hysteresis loop as shown changes its polarization direction upon application of an electric field that exceeds the coercive field EC (the hysteresis loop is shown with the voltage across the cell rather than the field along the abscissa axis for reasons of convenience). A saturation polarization PS is obtained whenever a memory cell is subjected to the nominal switching voltage VS. As the applied voltage is reduced to zero, the polarization will follow the hysteresis curve and end up at the remanence value PR. Depending on the polarity of the applied voltage, this zero field point may be at either the polarization state marked “1” or “0” in the figure, representing the two accessible logic states of the cell.
It should be noted that the shape of the hysteresis curve may depend on the speed at which the ferroelectric or electret material is cycled through the curve, as well as on the properties of the electrodes used to create the ferroelectric cell, and other factors (e.g. temperature). In particular, whereas many materials exhibit a hysteresis curve like the one in FIG. 4 when cycled at low speed, the apparent coercive field may increase and the apparent remanent polarization may become less as the voltage slew rate increases. Conversely, at very low slew rates the apparent coercive field may be strongly reduced or approach zero, especially in pure electrets with no ferroelectric contribution to the polarization. Furthermore, the presence or appearance of low-dielectric constant layers on the electrodes (e.g. due to chemical reactions at the electrode interface contacting the electret or ferroelectric material) shall increase the apparent coercive field. This implies that the terms “Coercive field” or “Coercive voltage” and “Remanent polarization” when employed in the following shall be understood to represent the corresponding quantitites in FIG. 4, as they appear under the specific operative conditions prevailing during applications of the teachings of the present document.
There are certain problems related to the polarizable materials that must be dealt with in order to make commercially viable devices, namely fatigue, imprint and disturb:
Fatigue results from repeated switching of the polarization direction in a given memory cell, whereby the switchable polarization progressively diminishes and ultimately becomes too small to allow proper operation of the memory. This phenomenon is well known and a range of remedies exist in the prior art. The present remedies are, however, generally material-specific and inadequate to provide fatigue resistance in commercially viable devices.
Imprint affects memory cells that are allowed to remain in a given logic state for a period of time. It manifests itself as a change in the switching properties whereby the hysteresis curve shifts so as to increase the coercive field perceived when switching the polarization direction to that opposite to the one where the material has resided during the imprinting period. In other words, the polarization has a tendency to become stuck in the direction where it is allowed to rest for some time.
Disturb is related to loss of polarization in a ferroelectric or electret memory cell which has been prepared in a given polarization state, when the cell is exposed to disturbing voltage pulses with a polarity in the opposite direction (i.e. a direction tending to polarize the cell in a sense opposite to that where it had been prepared). Even when the disturbing voltages are well below those corresponding to the coercive field, repeated exposure may cause the memory material to undergo partial switching leading to a loss of polarization. The extent of the partial switching depends on the material properties but may ultimately degrade the remanent polarization states Pr and −Pr to the extent that erroneous read results result.
Of the three problem areas mentioned above, fatigue and imprint are relevant in all types of ferroelectric or electret memory architectures, i.e. both in devices employing one or more transistors per memory cell (termed active matrix devices below) and in passive matrix devices as referred above. Remedies taught in prior art include strategies for postponing or reducing the onset of fatigue and imprint, as well as methods and apparatus for restoring the memory material in the fatigued and imprinted cells to a pristine or less-affected state. The latter procedures are generally collectively referred to as “refresh”.
Before proceeding, it should be emphasized that the present invention concerns a different type of refresh from that which is employed in prior art volatile memories such as different types of DRAMs, where memory cells typically are refreshed every 64 msec. This type of “traditional” memory refresh is performed to compensate for loss of stored charge in capacitors typically containing linear high-epsilon dielectrics, thus ensuring that the stored logic value in each memory cell is maintained. Typically, the whole memory is not refreshed at once since this cause a big surge in power and stall in data requests. To solve this, the refresh is split into one row/block of memory at each time resulting in a refresh period of e.g. 64 msec/number of rows.
In ferroelectric memories of the active matrix type, as opposed to the passive ones, problems like fatigue and imprint dominate and there is a need for refresh, both to retain the volatile polarization at a proper level but also to restore properties of the ferroelectric memory material.
In U.S. Pat. No. 5,550,770 (Kuroda), the memory device consists of arrays of ferroelectric memory cells, exemplified exclusively as containing ceramic ferroelectrics such as BaTiO or PZT, in active-matrix block addressing configurations of the 1T-NC type. In order to permit a simple Vs/2 selection scheme, N is a low number, e.g. N=8. Since it is the write operations that are considered to cause the need of refresh, there is a counter per memory block which is used to memorize the number of completed write operations before a forced refresh is carried out. This is carried out by first performing a destructive read of all cells of the memory block and temporarily storing the data elsewhere. Then all cells of the memory block are exposed to a voltage higher than the write voltage to achieve refresh by re-poling. Finally, the temporarily stored data are written back such that the polarization is switched only for those cells that are not already in the desired polarization state at that time. Beyond the specification that the refresh voltage shall be higher than that used in the standard read/write accesses, Kuroda provides no examples of, or teachings on the appropriate selection of refresh voltage pulse parameters, e.g. pulse shape, duration, degree of overvoltage, polarity shifts, if any, number or waiting periods.
In U.S. Pat. No. 5,777,921(Takata & al.) a device is disclosed with double counters for each memory block or memory cell, one for writing/reading one type of logic data and another for reading/writing the other type of logic data wherein refresh is initiated when either of the counters reach a predetermined value. Depending on which counter initiating the refresh the refresh voltages applied will look different such that the ferroelectric material will undergo a complete hysteresis cycle which is asserted to be a known method to restore the deterioration of the spontaneous electric field, i.e. to remove the imprinting effect. Since attention is paid to data content the refresh can be more efficient in terms of time for one type of logical data and there is no need to temporarily store data elsewhere during refresh. In the case of memory-cell based refresh, or small memory block, the redundancy of allocating cells for unnecessary refresh may be avoided but to the price of more counters.
In EP patent No. 0495572 (Moazzami & al.) a “higher than normal” voltage is used to exercise “the ferroelectric components” periodically to “refresh, or re-establish, the polarization state” and the refresh is further initiated after a predefined number of memory access cycles and/or after a predefined period of time.
In the found prior art no specific attention is paid to the problem of imprint at power up, i.e. after the memory has not been actively used for a period of time. Since such a period may be arbitrarily long there is a risk for substantial imprint, and in cases where the duration of the inactive period is not known a situation of maximum imprint has to be assumed and consequently dealt with.
In ferroelectric memories of the passive matrix type the absence of active elements in each cell facilitates higher integration density, lower power consumption and less complexity than in active matrix based counterparts. However, the problems of fatigue and imprint must be handled, as must the additional detrimental phenomenon of “disturb” referred above: Passive matrix memories lack active elements such as transistors that can connect/disconnect each memory cell from the rest of the matrix network during write/read/erase operations, and in certain operations involving single cell access it is inevitable that non-addressed memory cells are subjected to disturbing voltages. The magnitudes of such disturbing voltages on non-addressed cells depend on the timing and magnitudes of voltages applied to word- and bit-lines connecting to addressed as well as non-addressed cells in the matrix, and prior art literature contains teachings on how to avoid or reduce such complications by the use of voltage pulse protocols, i.e. precisely defined time- and amplitude-relationships between electrical potentials on all bit- and word-lines during operation of passive matrix addressed memory arrays. Examples of pulse protocols containing coordinated sequences of operations, e.g. imposing various sets of voltage pulses, connecting to sense amplifiers, grounding etc. can be found in U.S. Pat. No. 3,002,182 (Andersson), U.S. Pat. No. 4,169,258 (Tannas Jr.) and the published International Patent Application No. WO 02/05287 (Thompson et al.).
Unfortunately, even the most cleverly designed pulse protocols are subject to fundamental limitations, and the basic problem of disturb cannot in general be obviated by this means alone: As shown in the above quoted WO 02/05287, read- or write-related random access to single cells with a voltage Vs shall always imply subjecting non-addressed cells to disturbing voltages comparable to or larger than approximately Vs/3. In the following, protocols that expose non-addressed cells to a maximum disturb voltage of Vs/2 or Vs/3 shall be termed Vs/2 and Vs/3 protocols, respectively. Although Vs/3 is typically well below the voltage required to exceed the coercive field in the memory material in the cells, repeated exposure may lead to gradual loss of polarization and corresponding loss of information content. The disturb problem becomes particularly acute in advanced memory devices where it is sought to gain maximum advantage of the passive matrix addressing concept by using large matrices with typically thousands of crossing word lines and bit lines. This may cause non-addressed cells in the matrix to experience very large numbers of disturbing voltage pulses between each time they are accessed for write, read or erase operations. The net result of this may be that certain cells suffer a loss of polarization to an extent where the magnitude of the polarization switching during a read operation falls below the discrimination threshold between logic “0” and logic “1”.
One possibility for minimizing disturb in large passive matrix based memories is to divide each large matrix physically or electrically into a number of segments, wherein each such segment or “sub-matrix” can be seen as a passive matrix of its own. A suitable definition of a passive sub-matrix is that a memory cell being addressed in a certain sub-matrix, e.g. through a read or write operation, shall only give rise to disturb voltages on other memory cells in that same sub-matrix and not in other sub-matrices in the memory. Segmentation has been described to a limited extent in the prior art, with primary focus on reducing the effects of parasitic capacitances and sneak/relaxation currents which slow down and corrupt the electrical response of large passive matrix structures. Examples of segmentation/division are disclosed in the present applicant's pending patent application 20035225.
Exacerbating the problem of disturb in passive matrix addressed devices is the fact that imprint may start developing on very short timescales after the cell has been left in a polarized state, e.g. during a single pulse sequence under a protocol for normal write/read/erase operations. Thus, memory cells that have recently experienced an operation involving polarization reversal at one point in a voltage pulse protocol may retain significant imprint in the pre-reversal direction at a later stage in the same voltage pulse protocol, and consequently be extra prone to disturb. Since both imprint and disturb are typically affected by fatigue, it becomes apparent that successful strategies to handle these phenomena must take into account the strong interrelationships between all of them.